1/9 september 2001 n fully static operation 16 mhz (typ.) at v dd - v ss = 15v n standard ttl drive capability on q output n recirculation capability n three cascading modes : direct clocking for high speed operation delayed clocking for reduced clock drive requirements additional 1/2 stage for slows clocks n quiescent current specified up to 20v n 5v, 10v and 15v parametric ratings n input leakage current i i = 100na (max) at v dd = 18v t a = 25c n 100% tested for quiescent current n meets all requirements of jedec jesd13b " standard specifications for description of b series cmos devices" description the hcf4031b is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in dip package. this device is a static shift register that contains 64 d-type, master slave flip-flop stages and one stage which is a d-type master flip-flop only (referred to as a 1/2 stage). the logic level present at the data input is transferred into the first stage and shifted one stage at each positive going-clock transition. maximum clock frequencies up to 16 mhz (typ.) can be obtained. because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. the hcf4031b has a mode control input that, when in the high state, allows operation in the recirculation mode. the mode control input can also be used to select between two separate data sources. register packages can be cascaded and the clock lines driven directly for high speed operation. alternatively, a delayed clock output (cl d ) is provided that enables cascading register hcf4031b 64 stage static shift register pin connection order codes package tube t & r dip HCF4031BEY dip
hcf4031b 2/9 packages while allowing reduced clock drive fan-out and transition time requirements. a third cascading option makes use of the q output from the 1/2 stage, which is available on the next negative going transition of the clock after the q output occurs. this delayed output, like the delayed clock (cl d ), is used with clocks having slow rise and fall times. iinput equivalent circuit pin description functional diagram pin no symbol name and function 15 data in data input 2 clock clock input 10 mode con- trol mode control input 9 clock delayed delayed clock output 1 recircu- latio in recirculation data in 5, 6, 7 q, q , q data outputs 3, 4, 11, 12, 13, 14 nc not connected 8 v ss negative supply voltage 16 v dd positive supply voltage
hcf4031b 3/9 truth tables input control circuit typical stage output from q x : dont care nc : no change logic diagram absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. all voltage values are referred to v ss pin voltage. data recirculation mode control bit into stage 1 hxlh lxll xhhh xlhl data clock data+1 ll hh xnc data+64 clock data+64.5 ll hh xnc symbol parameter value unit v dd supply voltage -0.5 to +22 v v i dc input voltage -0.5 to v dd + 0.5 v i i dc input current 10 ma p d power dissipation per package 200 mw power dissipation per output transistor 100 mw t op operating temperature -55 to +125 c t stg storage temperature -65 to +150 c
hcf4031b 4/9 recommended operating conditions dc specifications the noise margin for both "1" and "0" level is: 1v min. with v dd =5v, 2v min. with v dd =10v, 2.5v min. with v dd =15v symbol parameter value unit v dd supply voltage 3 to 20 v v i input voltage 0 to v dd v t op operating temperature -55 to 125 c symbol parameter test condition value unit v i (v) v o (v) |i o | ( m a) v dd (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. i l quiescent current 0/5 5 0.04 5 150 150 m a 0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000 v oh high level output voltage 0/5 <1 5 4.95 4.95 4.95 v 0/10 <1 10 9.95 9.95 9.95 0/15 <1 15 14.95 14.95 14.95 v ol low level output voltage 5/0 <1 5 0.05 0.05 0.05 v 10/0 <1 10 0.05 0.05 0.05 15/0 <1 15 0.05 0.05 0.05 v ih high level input voltage 0.5/4.5 <1 5 3.5 3.5 3.5 v 1/9 <1 10 7 7 7 1.5/13.5 <1 15 11 11 11 v il low level input voltage 4.5/0.5 <1 5 1.5 1.5 1.5 v 9/1 <1 10 3 3 3 13.5/1.5 <1 15 4 4 4 i oh output drive current (source) q, q , q cl d 0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1 ma 0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36 0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4 i ol output sink current q 0/5 0.4 <1 5 1.74 4 1.43 1.43 ma 0/10 0.5 <1 10 4.42 10.4 3.74 3.74 0/15 1.5 <1 15 11.56 27.2 9.52 9.52 i ol output sink current q , q, cl d 0/5 0.4 <1 5 0.44 1 0.36 0.36 ma 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 0/15 1.5 <1 15 3.0 6.8 2.4 2.4 i i input leakage current 0/18 any input 18 10 -5 0.1 1 1 m a c i input capacitance any input 5 7.5 pf
hcf4031b 5/9 dynamic electrical characteristics (t amb = 25c, c l = 50pf, r l = 200k w , t r = t f = 20 ns) (*) typical temperature coefficient for all v dd value is 0.3 %/c. (1) if more than one unit is cascaded, in the parallel clocked application, trcl should be made less than or equal to the sum o f the propagation delay at 50pf and the transmission time of the output driving stage. (2) maximum clock frequency for cascaded units; a) using delayed clock feature in recirculation mode : 1 f max = ???????????????????????? where n = number of packages (n-1) cld prop. delay + q prop. delay + setup time b) not using delayed clock : 1 f max = ?????????????? propagation delay + setup time symbol parameter test condition value (*) unit v dd (v) min. typ. max. t phl, t plh, t plh propagation delay time : clock to q, clock to q 5 250 500 ns 10 110 220 15 90 180 t phl, t plh, t phl propagation delay time : clock to q, clock to q 5 190 380 ns 10 80 160 15 65 130 propagation delay time : clock to cl d 5 100 200 ns 10 50 100 15 40 80 t thl , t tlh transition time : (any output, except q) 5 100 200 ns 10 50 100 15 40 80 t thl transition time : (q) 550100 ns 10 25 50 15 20 40 t setup data setup time 5 30 60 ns 10 15 30 15 10 20 t hold data hold time 5 30 60 ns 10 15 30 15 10 20 t w clock pulse width 5 120 240 ns 10 50 100 15 40 80 f max (2) maximum clock input frequency 524 mhz 10 5 10 15 6 12 t r , t f (1) clock input rise or fall time 51000 m s 10 1000 15 200
hcf4031b 6/9 typical applications cascading using direct clocking for high speed operation (see clock rise and fall time requirement) cascading using delayed clocking for reduced clock drive requirements cascading using half clock pulse delayed data output (q) to permit use of slow rise and fall time clock inputs
hcf4031b 7/9 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = 200k w r t = z out of pulse generator (typically 50 w )
hcf4031b 8/9 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
hcf4031b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 9/9
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